The present invention relates to a semiconductor memory device which is very small in size and has a large storage capacity, and more specifically to stacked capacitor (STC) cells of a dynamic random access memory (DRAM) that is adapted to being integrated highly densely.
The integration degree of a DRAM has quadrupled in every three years, and mega-bit memories have already been mass-produced. The degree of integration is heightened by decreasing the sizes of elements. However, reduction in the storage capacity accompanying the decrease in sizes has invited problems with regard to decrease in the signal-to-noise (S/N) ratio, inversion of signals caused by incident alpha particles and maintenance of reliability.
As a memory cell capable of increasing the storage capacity, therefore, a stacked capacitor cell in which part of a storage capacity portion is overlapped on a switching transistor or on an element isolating oxide film disclosed in Japanese Patent Publication No. 55258/1986 has been expected to substitute for the existing planar type capacitor.
FIG. 2 is a layout plan view of a conventional STC cell, wherein the reference numeral 2.1 denotes active regions where a channel region and an impurity diffusion layer will be formed to constitute a switching transistor, 2.2 denotes word lines that serve as gate electrodes for the switching transistor, 2.3 denotes contact holes through which the bit lines 2.8 come into contact with the diffusion layer in the substrate, 2.4 denote conductive layers that serve as pads for connecting the bit lines and the diffusion layer together, 2.5 denote contact holes for connecting the lower electrodes 2.6 of the storage capacity portions to the diffusion layer, 2.7 denotes plane electrodes, and 2.8 denotes bit lines.
With the STC cell, the storage capacity portion indicated by the lower electrode 2.6 of the storage capacity portion can be extended onto the word line, making it possible to realize a storage capacity which is considerably greater than that of a planar type cell in which only the surface of the substrate is utilized as a storage capacity portion. Therefore, even a small cell area employed for the mega-bit DRAM's is capable of producing a storage capacity which is large enough for operating the circuit. With the conventional planar type cell having the same cell area as the above-mentioned cell, however, it is difficult to obtain a required capacity even if thickness of the insulating film is reduced.
In fact, however, even the STC cell has many problems as will be described below in detail in conjunction with a sectional view of FIG. 4. The STC cell is fabricated through the later-described steps. First, on a single crystalline semiconductor substrate 4.1 is grown a relatively thick oxide film 4.2 for electrically isolating the individual elements by the widely known thermal oxidation method. The film thickness ranges from about 100 to about 1000 nm. Then, a gate insulating film 4.3 for forming a switching transistor is grown by the widely known thermal oxidation method. The film thickness decreases with the reduction in the size of element and, usually, ranges from 10 to 50 nm. Polycrystalline silicon containing impurities is deposited and is delineated by the widely known photolithograph method and the dry etching method to form a word line 4.4. Using the delineated word line as a mark, furthermore, impurities having a conductivity type different from that of the substrate 4.1 are introduced by the widely known ion implantation method thereby to form an impurity diffusion layer 4.5. It need not be pointed out that the heat treatment is necessary for activating the impurity diffusion layer. Then, in order to form a storage capacity portion, polycrystalline silicon 4.7 having the same type of conductivity is deposited by the widely known CVD chemical vapor deposition method so as to come into contact with the impurity diffusion layer in the substrate. As will be obvious from the plan view of FIG. 2, the polycrystalline silicon 4.7 is formed also on the word line 4.4 and on the element isolating film 4.2. Therefore, the area of the storage capacity portion increases and, hence, a large storage capacity is maintained.
At this moment, furthermore, polycrystalline silicon is also formed simultaneously even on a place where the contact hole (2.3 in FIG. 2) is formed to connect the bit line 4.11 to the impurity diffusion layer 4.5. Even when the distance between the word lines is small, therefore, the bit line can be connected to the diffusion layer via the polycrystalline silicon layer (2.4 in FIG. 2) without causing the bit line 4.11 and the word line 4.4 to be short-circuited to each other. Here, the reference numerals 4.6 and 4.10 denote interlayer insulating films.
In the STC cell of the conventional structure, however, a pad conductor layer 2.4 must be exposed when a plate electrode 4.9 is to be formed. This is because, the bit line 4.11 and the pad conductor layer must come into contact with each other through this place. In delineating the plate electrode, therefore, a highly sophisticated technology is required to stop the pad conductor layer from being etched accompanying the dry etching of the plate electrode using a very thin capacitor insulating film 4.8 that is formed also on the surface of the pad conductor layer, such that the pad conductor layer will not be ground.
In addition to the above-mentioned problem involved in the production, there exists another essential problem in that it is difficult to decrease the cell area so far as the above-mentioned cell structure is employed. This stems from the fact that a sufficiently large distance must be maintained between the plate electrode 4.9 and the pad conductor layer 2.4 so that the two will not come into contact with each other. It is allowable to omit the pad conductor layer 2.4. In this case, however, the distance between the word lines must be increased to prevent the short-circuiting between the bit lines 4.11 and the word lines 4.4, making it difficult to decrease the cell areas.
With the conventional STC structure as described above, it is difficult to decrease the cell area. Namely, the conventional STC cells are not applicable for very highly integrated DRAM's of 4-mega-bits or greater.
An STC structure free from these problems has been taught in Japanese Utility Model Laid-Open No. 178894/1980. FIG. 3 is a layout plan view of this STC cells. To simplify the drawing, there is shown no lower electrode of the storage capacity portion or plate electrode that is arranged on the contact hole 3.4 in the memory portion.
The feature of this structure resides in that in the active region 3.1, the bit line 3.5 is not arranged on a portion where a contact hole 3.4 of the memory portion is opened. It need not be pointed out that the bit line 3.5 is in contact with the impurity diffusion layer of the substrate through the contact hole 3.3. The storage capacity portion is formed after the bit lines have been formed. In forming the plate electrodes, therefore, there is no need of exposing the bit line contact portions that are shown in FIGS. 2 and 4. Reference numerals 3.2 denote lead wires.
That is, the plate electrodes need simply cover the memory cell portions.
According to such a cell structure in which the area of the lower electrode of the storage capacity portion is not limited by the delineation of plate electrode, a large storage capacity can be realized yet decreasing the cell area.
Even with this structure, however, great difficulty is involved to shorten the distance between the bit lines if bit lines 3.5 arranged in parallel are not simply overlapped on the contact holes 3.4 of the memory portion in the active region 3.1. In the layout of FIG. 3, the distance increases between the bit lines imposing limitation on reducing the cell area.
A memory cell structure which allows several layers of storage capacity portions to be laminated in order to further increase the storage capacity is proposed, as described in Japanese Patent Laid-Open No. 58958/1988.
This type of memory cell is shown in FIG. 17. The memory cell having this structure theoretically enables the storage capacity to be increased to any extent by laminating charge storage electrodes 18 in many layers. However, when the actual capability in the fabricating technique such as, for example, the focal depth of an exposing apparatus is taken into consideration, generation of a large difference in level is unfavorable. The allowable difference in level is about 0.5 .mu.m in 64 mega-bit DRAM's using 0.3 .mu.m technique. More specifically, in the case of the structure shown in FIG. 17, if it is assumed that the thickness of each electrode is 0.1 .mu.m, it is considered that lamination is limited to two storage electrodes 18 and three plate electrodes 111. The number of opposing faces of the storage electrodes 18 and the plate electrodes 111 designed by the above-described structure of the electrodes is four at maximum. In 64 mega-bit DRAM's, the cell area is inferred to be about 1 .mu.m.sup.2. If it is assumed that the area of 1.times.1 .mu.m.sup.2 is used as the storage capacity as it is and that 40% of ineffective region exists for connecting the upper and lower electrodes, the effective area as a capacitor having a structure shown in FIG. 17 is obtained as follows: EQU 1 .mu.m.times.1 .mu.m.times.4 faces.times.0.6=2.4 .mu.m.sup.2 ( 1)
In order to realize the above-described structure, at least two cycles of steps of laminating storage electrodes, at least two cycles of steps of forming electrode insulating films, at least one cycle of processing step for connecting upper and lower electrodes, step of forming a capacitor insulating film 19, step of forming a plate electrode 111, etc. are required, thereby disadvantageously greatly increasing the number of steps.
In FIG. 17, the reference numeral 11 represents an Si substrate, 12 an element isolating film, 14 a word line, 16 a bit line, 112 an interlayer insulating film and 113 an impurity diffusion layer.